This invention relates to a semiconductor integrated circuit and a manufacturing method thereof wherein an insulating isolation region has a high density and a small parasitic capacitance can be obtained.
Conventional insulating isolation region-forming methods in which grooves filled with CVD SiO.sub.2 are utilized have been proposed. A typical manufacturing process for a bipolar LSI using the above mentioned method are illustrated in FIGS. 6A-6F inclusive.
The process begins with the formation of an n+ type buried region 2 by diffusing arsenic over a depth of 1 micron in a p-type silicon substrate 1, and is followed by the formation of an n-type epitaxial layer 3 having a thickness of 1 micron. Then, an SiO.sub.2 layer 4 having a thickness of 1.2 microns is formed by a CVD method and portions thereof are removed from the isolation region by means of photolithographic techniques (FIG. 6A).
The Si portion exposed by performing the abovementioned steps is etched off by utilizing the CVD SiO.sub.2 layer as an etching mask to form a groove 5 having a depth of 2.5-3.5 microns and a width of 1.2 microns. Then, a boron ion implantation process is carried out to form a channel stopper region 6 on the bottom of said groove by using the CVD SiO.sub.2 layer 4 as a mask (FIG. 6B).
An SiO.sub.2 layer 7 having a thickness of 1.4 microns is deposited at 800.degree. C. by means of a thermal decomposition method employing SiH.sub.2 Cl.sub.2 and N.sub.2 O gases to fill the groove 5 with the SiO.sub.2 layer 7 (FIG. 6C). A photoresist layer is then formed on the substrate and which is later removed by means of a dry etching process except at the indented regions on which the photoresist layer is left at 8 to form a flat upper surface (FIG. 6D).
The photoresist 8 and SiO.sub.2 7 layers are then removed to leave flat surfaces of the isolation SiO.sub.2 layer 7 and the epitaxial layer 3 (FIG. 6E). A field SiO.sub.2 layer 9 having a thickness of 0.6 micron, n+ type collector region 10, p+ type base region 11, and n+type emitter region 12 are formed by performing a selective oxidation method. In this case, referring to FIG. 6F, an indented region 13 is formed due to the higher etching speed at which the SiO.sub.2 layer 7 occupying the groove 5 is etched by hydrofluoric acid.
In the above-mentioned process, when the groove 5 is occupied by the SiO.sub.2 layer 7 as shown by FIG. 7A, a region 15 in the Si.sub.2 layer 7 where the etching speed by hydrofluoric acid is higher is formed if the ratio of the groove depth d and its width w, or d/w, exceeds 2 to 1. Therefore, an indented region 16 is formed on the isolation region during the transistor forming processes after the flat surface is provided, and because of this, the formation of a precise pattern thereon cannot be carried out.
Furthermore, if a wider isolation groove is made, since the thickness of the SiO.sub.2 layer 7 corresponds to the depth of the groove, the deposition of the SiO.sub.2 layer and the provision of the flat upper surface is troublesome.
And, when the field SiO.sub.2 layer 7 is formed with a selective oxidation process, the substrate has to be heated and because of this, the arsenic in the n+ type buried region 2 could diffuse into the epitaxial layer 3, and the boron in the p+ type channel stopper region 6 could diffuse to bring the n+ buried region 2 close to the channel stopper region 6 thereby increasing the capacitance between the collector and the substrate.
Furthermore, when voltage is applied between the transistor collectors 10, the isolation depth has to be relatively deep in order to prevent the contact of the depletion layer with the collector region 10. If a wider isolation groove is provided, the depth may be made shallower, but this requires the provision of a thicker SiO.sub.2 layer 7.
Finally, after the isolation region-forming process is performed, even if the surfaces of the SiO.sub.2 layer 7 and the silicon substrate are flat, an entire layer of the SiO.sub.2 layer 7 is etched off to expose the silicon substrate at the side wall of isolation region as shown at 1a in FIG. 7B, and due to this, the transistor characteristics may be degenerated.